module bps(clk, rst,Count_Sig, bps_clk);
input clk;
input rst;
input Count_Sig;
output bps_clk;
reg [12:0]Count_BPS;
	 always @(posedge clk or negedge rst)
	    if(!rst)
		     Count_BPS<=13'd0;
		 else if(Count_BPS==13'd5207)
		     Count_BPS<=13'd0;
		 else if(Count_Sig)
		     Count_BPS<=Count_BPS+1'b1;
		 else
		     Count_BPS<=13'd0;
	 assign bps_clk=(Count_BPS==12'd2604)?1'b1:1'b0;
endmodule